Semiconductor device

ABSTRACT

A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. 
     The semiconductor device includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a semiconductor layer, and a first conductive layer. The second insulating layer is positioned over the first insulating layer and the island-shaped semiconductor layer is positioned over the second insulating layer. The second insulating layer has an island shape having an end portion outside a region overlapping with the semiconductor layer. The fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, is in contact with part of a top surface of the semiconductor layer, and is in contact with the first insulating layer outside the end portion of the second insulating layer. The semiconductor layer contains a metal oxide, the second insulating layer and the third insulating layer contain an oxide, the first insulating layer contains a metal oxide or a nitride, and the fourth insulating layer contains a metal nitride.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application PCT/IB2018/058226, filed on Oct. 23, 2018, which is incorporated by reference and claims the benefit of a foreign priority application filed in Japan on Nov. 2, 2017, as Application No. 2017-213017.

TECHNICAL FIELD

One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a display device. One embodiment of the present invention relates to a method for manufacturing a semiconductor device or a display device.

Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input/output device, a driving method thereof, and a manufacturing method thereof. A semiconductor device generally means a device that can function by utilizing semiconductor characteristics.

BACKGROUND ART

As a semiconductor material that can be used in a transistor, an oxide semiconductor using a metal oxide has been attracting attention. For example, Patent Document 1 discloses a semiconductor device which achieves increased field-effect mobility (simply referred to as mobility or μFE in some cases) by stacking a plurality of oxide semiconductor layers, containing indium and gallium in an oxide semiconductor layer serving as a channel in the plurality of oxide semiconductor layers, and making the proportion of indium higher than the proportion of gallium.

A metal oxide that can be used for a semiconductor layer can be formed by a sputtering method or the like, and thus can be used for a semiconductor layer of a transistor included in a large display device. In addition, capital investment can be reduced because part of production equipment for a transistor using polycrystalline silicon or amorphous silicon can be retrofitted and utilized. A transistor using a metal oxide has field-effect mobility higher than that in the case where amorphous silicon is used; therefore, a high-performance display device provided with driver circuits can be obtained.

Patent Document 2 discloses a thin film transistor in which a source region and a drain region use an oxide semiconductor film including a low-resistance region containing at least one kind in a group consisting of aluminum, boron, gallium, indium, titanium, silicon, germanium, tin, and lead as a dopant.

PRIOR ART DOCUMENTS Patent Documents

[Patent Document 1] Japanese Published Patent Application No. 2014-7399

[Patent Document 2] Japanese Published Patent Application No. 2011-228622

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

One object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object is to provide a semiconductor device having stable electrical characteristics. Another object of one embodiment of the present invention is to provide a highly reliable display device.

Note that the descriptions of these objects do not disturb the existence of other objects. Note that in one embodiment of the present invention, there is no need to achieve all of these objects. Note that objects other than them can be derived from the descriptions of the specification, the drawings, the claims, and the like.

Means for Solving the Problems

One embodiment of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a semiconductor layer, and a first conductive layer. The second insulating layer is positioned over the first insulating layer. The semiconductor layer is positioned over the second insulating layer and has an island shape. The third insulating layer and the first conductive layer are stacked over the semiconductor layer. The second insulating layer has an island shape having an end portion outside a region overlapping with the semiconductor layer. The fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, is in contact with part of a top surface of the semiconductor layer, and is in contact with the first insulating layer outside the end portion of the second insulating layer. The semiconductor layer includes a metal oxide. The second insulating layer and the third insulating layer include an oxide. The first insulating layer includes a metal oxide or a nitride. The fourth insulating layer includes a metal nitride.

In the above, the fourth insulating layer preferably contains aluminum.

In the above, the first insulating layer preferably contains at least one of aluminum and hafnium and oxygen.

In the above, the second insulating layer and the semiconductor layer preferably have substantially the same top surface shape.

In the above, the end portion of the second insulating layer preferably has a portion positioned outside a region overlapping with the first conductive layer.

In the above, the end portion of the second insulating layer preferably has a portion positioned in a region overlapping with the first conductive layer.

In the above, a second conductive layer is preferably included under the first insulating layer, and the second conductive layer preferably has a region overlapping with both the semiconductor layer and the first conductive layer.

In the above, the end portion of the second insulating layer preferably has a portion positioned outside a region overlapping with the second conductive layer. The end portion of the second insulating layer preferably has a portion positioned in a region overlapping with the second conductive layer.

Effect of the Invention

With one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. A semiconductor device having stable electrical characteristics can be provided. A highly reliable display device can be provided.

Note that the descriptions of these effects do not disturb the existence of other effects. Note that in one embodiment of the present invention, there is no need to achieve all of these effects. Note that effects other than them can be derived from the descriptions of the specification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C A structure example of a transistor.

FIGS. 2A to 2C A structure example of a transistor.

FIGS. 3A to 3C A structure example of a transistor.

FIGS. 4A and 4B A structure example of a transistor.

FIGS. 5A to 5C Structure examples of a transistor.

FIGS. 6A to 6C Structure examples of a pixel.

FIGS. 7A to 7C Diagrams illustrating a method for manufacturing a transistor.

FIGS. 8A to 8C Diagrams illustrating a method for manufacturing a transistor.

FIGS. 9A and 9B Diagrams illustrating a method for manufacturing a transistor.

FIGS. 10A and 10B Top views of display devices.

FIG. 11 A cross-sectional view of a display device.

FIG. 12 A cross-sectional view of a display device.

FIG. 13 A cross-sectional view of a display device.

FIG. 14 A cross-sectional view of a display device.

FIG. 15 A cross-sectional view of a display device.

FIGS. 16A to 16C A block diagram and circuit diagrams of a display device.

FIG. 17 A block diagram of a display device.

FIGS. 18A and 18B A structure example of a display module.

FIGS. 19A to 19E Structure examples of electronic devices.

FIGS. 20A to 20G Structure examples of electronic devices.

FIGS. 21A to 21D Structure examples of electronic devices.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments will be described with reference to drawings. Note that the embodiments can be implemented with many different modes, and it will be readily appreciated by those skilled in the art that modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Thus, the present invention should not be interpreted as being limited to the following description of the embodiments.

Furthermore, in each drawing described in this specification, the size, the layer thickness, or the region of each component is exaggerated for clarity in some cases.

Note that ordinal numbers such as “first”, “second”, and “third” used in this specification are used in order to avoid confusion among components, and the terms do not limit the components numerically.

In this specification, terms for describing arrangement, such as “over” and “under”, are used for convenience in describing a positional relation between components with reference to drawings. Furthermore, the positional relation between components is changed as appropriate in accordance with a direction in which each component is described. Thus, terms for the description are not limited to those used in this specification, and description can be made appropriately depending on the situation.

Furthermore, in this specification and the like, functions of a source and a drain of a transistor might be switched when a transistor of opposite polarity is employed or the direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be used interchangeably.

Furthermore, in this specification and the like, “electrically connected” includes the case where connection is made through an “object having any electric function”. Here, there is no particular limitation on the “object having any electric function” as long as electric signals can be transmitted and received between the connected components. Examples of the “object having any electric function” include a switching element such as a transistor, a resistor, an inductor, a capacitor, and other elements having a variety of functions as well as an electrode and a wiring.

In this specification and the like, the term “film” and the term “layer” can be interchanged with each other. For example, in some cases, the term “conductive layer” and the term “insulating layer” can be interchanged with the term “conductive film” and the term “insulating film”, respectively.

Unless otherwise specified, an off-state current in this specification and the like refers to a drain current of a transistor in an off state (also referred to as a non-conducting state or a cutoff state). Unless otherwise specified, an off state refers to, in an n-channel transistor, a state where the voltage Vgs between its gate and source is lower than the threshold voltage Vth (in a p-channel transistor, higher than Vth).

In this specification and the like, a display panel which is one embodiment of the display device has a function of displaying (outputting) an image or the like on (to) a display surface. Thus, the display panel is one embodiment of an output device.

In this specification and the like, a substrate of a display panel to which a connector such as an FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package) is attached, or a substrate on which an IC is mounted by a COG (Chip On Glass) method or the like is referred to as a display panel module, a display module, or simply a display panel or the like in some cases.

Note that in this specification and the like, a touch panel which is one embodiment of the display device has a function of displaying an image or the like on a display surface and a function of a touch sensor capable of sensing the contact, press, approach, or the like of a sensing target such as a finger or a stylus with or to the display surface. Therefore, the touch panel is one embodiment of an input/output device.

A touch panel can be referred to as, for example, a display panel (or a display device) with a touch sensor or a display panel (or a display device) having a touch sensor function. A touch panel can include a display panel and a touch sensor panel. Alternatively, a touch panel can have a function of a touch sensor at the inside or on a surface of the display panel.

Furthermore, in this specification and the like, a substrate of a touch panel to which a connector or an IC is attached is referred to as a touch panel module, a display module, or simply a touch panel or the like in some cases.

Embodiment 1

In this embodiment, a semiconductor device and a display device of one embodiment of the present invention and a manufacturing method thereof will be described.

One embodiment of the present invention is a transistor including, over a formation surface, a semiconductor layer in which a channel is formed, a gate insulating layer (also referred to as a third insulating layer) over the semiconductor layer, and a gate electrode over the gate insulating layer. The semiconductor layer preferably contains a metal oxide exhibiting semiconductor characteristics (hereinafter also referred to as an oxide semiconductor).

The gate electrode and the gate insulating layer preferably have substantially the same top surface shape. In other words, the gate electrode and the gate insulating layer are preferably processed so that their side surfaces are continuous. For example, the gate electrode and the gate insulating layer can be formed in such a manner that an insulating film to be the gate insulating layer and a conductive film to be the gate electrode are stacked and then processed with the use of one etching mask. Alternatively, the gate insulating layer may be formed by processing the insulating film with the use of the gate electrode that has been processed in advance as a hard mask.

The semiconductor layer includes a channel formation region where a channel can be formed and a pair of low-resistance regions functioning as a source region and a drain region. The channel formation region is a region of the semiconductor layer that overlaps with the gate electrode. The low-resistance region is a region having a lower resistance than the channel formation region.

An insulating layer containing a metal nitride (also referred to as a fourth insulating layer) is provided in contact with a surface of the low-resistance region of the semiconductor layer. When the insulating layer containing a metal nitride is provided in contact with the semiconductor layer, an effect of increasing the conductivity of the low-resistance region is attained. Furthermore, heat treatment is preferably performed while the insulating film containing a metal nitride is provided in contact with the semiconductor layer because a reduction in the resistance is further promoted.

It is particularly preferable that the metal nitride contain aluminum. For example, an aluminum nitride film formed by a reactive sputtering method using aluminum as a sputtering target and a nitrogen-containing gas as a deposition gas can be a film having both an extremely high insulating property and an extremely high blocking property against hydrogen and oxygen when the flow rate of the nitrogen gas with respect to the total flow rate of the deposition gas is appropriately controlled. Therefore, when such an insulating film containing a metal nitride is provided in contact with the semiconductor layer, the resistance of the semiconductor layer can be reduced, and release of oxygen from the semiconductor layer and diffusion of hydrogen into the semiconductor layer can be favorably prevented.

In the case where aluminum nitride is used as the metal nitride, the thickness of the insulating film containing the aluminum nitride is preferably greater than or equal to 5 nm. A film with such a small thickness can also have both a high blocking property against hydrogen and oxygen and a function of reducing the resistance of the semiconductor layer. Note that there is no upper limit of the thickness of the insulating layer; however, the thickness is preferably less than or equal to 500 nm, further preferably less than or equal to 200 nm, still further preferably less than or equal to 50 nm in consideration of productivity.

An insulating layer containing an oxide (also referred to as a second insulating layer) is preferably provided in contact with a bottom surface of the semiconductor layer. When the second insulating layer containing an oxide is provided in contact with the semiconductor layer, oxygen that is released by heating can be supplied to the semiconductor layer effectively and oxygen vacancies in the semiconductor layer can be filled.

In one embodiment of the present invention, the second insulating layer has an island shape. Moreover, an insulating layer having a high blocking property against water, hydrogen, and oxygen (also referred to as a first insulating layer) is provided under the second insulating layer. Furthermore, a side surface of an end portion and a top surface of the second insulating layer are covered with the insulating layer containing a metal nitride (the fourth insulating layer). The first insulating layer and the fourth insulating layer are in contact with each other in a region outside the end portion of the island-shaped second insulating layer, so that the second insulating layer, the semiconductor layer, and the like can be surrounded by (sealed with) the first insulating layer and the fourth insulating layer. Accordingly, oxygen released from the second insulating layer can be effectively inhibited from being released to the outside, and most of the oxygen can be supplied to the semiconductor layer.

Here, when extremely excessive oxygen is supplied to the semiconductor layer, the transistor characteristics might be adversely affected. However, in this structure, the amount of oxygen that can be supplied to the semiconductor layer can be controlled by changing the area of the second insulating layer processed into an island shape. The area can be designed as appropriate depending on the amount of oxygen that can be released from the second insulating layer, the area of the semiconductor layer that overlaps with the second insulating layer, the thickness of the second insulating layer, or the like.

Employing such a structure makes it possible to provide a semiconductor device having excellent electrical characteristics and high reliability.

More specific examples will be described below with reference to drawings.

Structure Example 1

FIG. 1(A) is a top view of a transistor 100, FIG. 1(B) corresponds to a cross-sectional view of a cut plane taken along a dashed-dotted line A1-A2 in FIG. 1(A), and FIG. 1(C) corresponds to a cross-sectional view of a cut plane taken along a dashed-dotted line B1-B2 in FIG. 1(A). Note that in FIG. 1(A), some components of the transistor 100 (a gate insulating layer and the like) are not illustrated. Furthermore, the direction of the dashed-dotted line A1-A2 and the direction of the dashed-dotted line B1-B2 may be referred to as a channel length direction and a channel width direction, respectively. Some components are not illustrated in some cases in top views of transistors also in the following drawings, as in FIG. 1(A).

The transistor 100 is provided over a substrate 102 and includes an insulating layer 103, an insulating layer 104, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 116, an insulating layer 118, and the like. The insulating layer 104 is provided over the insulating layer 103, and the semiconductor layer 108 is provided over the insulating layer 104. The insulating layer 110, the metal oxide layer 114, and the conductive layer 112 are stacked in this order over the semiconductor layer 108. The insulating layer 116 is provided to cover a top surface and a side surface of the insulating layer 104, a top surface and a side surface of the semiconductor layer 108, a side surface of the insulating layer 110, a side surface of the metal oxide layer 114, and a top surface and a side surface of the conductive layer 112. The insulating layer 118 is provided to cover the insulating layer 116.

Part of the conductive layer 112 functions as a gate electrode. Part of the insulating layer 110 functions as a gate insulating layer. The transistor 100 is what is called a top-gate transistor, in which the gate electrode is provided over the semiconductor layer 108.

The semiconductor layer 108 preferably contains a metal oxide.

The semiconductor layer 108 preferably contains indium, M (M is one or more kinds selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc, for example. In particular, M is preferably aluminum, gallium, yttrium, or tin.

It is particularly preferable to use an oxide containing indium, gallium, and zinc for the semiconductor layer 108.

The semiconductor layer 108 may have a stacked-layer structure in which layers with different compositions, layers with different crystallinities, or layers with different impurity concentrations are stacked.

The semiconductor layer 108 includes a region overlapping with the conductive layer 112 and low-resistance regions 108 n between which the region is interposed. The insulating layer 116 is provided in contact with the regions 108 n. The region of the semiconductor layer 108 that overlaps with the conductive layer 112 functions as a channel formation region of the transistor 100. The regions 108 n function as a source region and a drain region of the transistor 100.

As illustrated in FIGS. 1(A) and 1(B), the transistor 100 may include a conductive layer 120 a and a conductive layer 120 b over the insulating layer 118. One of the conductive layer 120 a and the conductive layer 120 b functions as a source electrode, and the other functions as a drain electrode. The conductive layer 120 a and the conductive layer 120 b are electrically connected to the regions 108 n through an opening portion 141 a and an opening portion 141 b, respectively, which are provided in the insulating layer 118 and the insulating layer 116.

The conductive layer 112, the metal oxide layer 114, and the insulating layer 110 have substantially the same top surface shape.

Note that in this specification and the like, the expression “having substantially the same top surface shape” means that at least outlines of stacked layers partly overlap with each other. For example, the case of processing or partly processing an upper layer and a lower layer with the use of the same mask pattern is included. However, in some cases, the outlines do not completely overlap with each other and the upper layer is positioned on the inner side of the lower layer or the upper layer is positioned on the outer side of the lower layer; such a case is also represented by the expression “having substantially the same top surface shape”.

The metal oxide layer 114 positioned between the insulating layer 110 and the conductive layer 112 functions as a barrier film that prevents oxygen contained in the insulating layer 110 from being diffused into the conductive layer 112 side. For the metal oxide layer 114, a material that is less likely to transmit oxygen than at least the insulating layer 110 can be used, for example.

Even in the case where a metal that is likely to absorb oxygen, such as aluminum or copper, is used for the conductive layer 112, the metal oxide layer 114 can prevent diffusion of oxygen from the insulating layer 110 into the conductive layer 112. Furthermore, even in the case where the conductive layer 112 contains hydrogen, supply of hydrogen from the conductive layer 112 to the semiconductor layer 108 through the insulating layer 110 is inhibited. Consequently, the carrier density of the channel formation region of the semiconductor layer 108 can be extremely low.

For the metal oxide layer 114, an insulating material or a conductive material can be used. When the metal oxide layer 114 has an insulating property, the metal oxide layer 114 functions as part of the gate insulating layer. In contrast, when the metal oxide layer 114 has conductivity, the metal oxide layer 114 functions as part of the gate electrode.

In particular, an insulating material having a higher permittivity than silicon oxide is preferably used for the metal oxide layer 114. It is particularly preferable to use an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like.

The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an aluminum oxide film is formed using a sputtering apparatus, formation in an atmosphere containing an oxygen gas enables oxygen to be added to the insulating layer 110 and the semiconductor layer 108 in a favorable manner. An aluminum oxide film formed using a sputtering apparatus is favorable because the film density can be increased.

As the insulating layer 116, an insulating film containing a metal nitride can be used. The insulating layer 116 preferably contains at least one of metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium and nitrogen. In particular, a film containing aluminum and nitrogen is preferable because of its extremely high insulating property.

In the case of using an aluminum nitride film as the insulating layer 116, it is preferable to use a film that satisfies the composition formula AlN_(x) (x is a real number greater than 0 and less than or equal to 2, and x is preferably a real number greater than 0.5 and less than or equal to 1.5). In that case, a film having an excellent insulating property and high thermal conductivity can be obtained, and thus dissipation of heat generated in driving the transistor 100 can be increased.

Alternatively, an aluminum titanium nitride film, a titanium nitride film, or the like can be used as the insulating layer 116.

The region 108 n is part of the semiconductor layer 108 and is a region having a lower resistance than the channel formation region.

Here, in the case where a metal oxide film containing indium is used as the semiconductor layer 108, a region where metal indium is precipitated or a region having a high indium concentration is sometimes formed in the region 108 n in the vicinity of the interface with the insulating layer 116. Such a region can be observed by an analysis method such as X-ray photoelectron spectroscopy (XPS) in some cases.

The region 108 n can be regarded as a region having a higher carrier density than the channel formation region, a region having a higher oxygen defect density than the channel formation region, or an n-type region.

As each of the insulating layer 104 and the insulating layer 110 that are in contact with the channel formation region of the semiconductor layer 108, an oxide film is preferably used. For example, an oxide film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film can be used. Accordingly, by heat application treatment or the like during the manufacturing process of the transistor 100, oxygen released from the insulating layer 104 and the insulating layer 110 can be supplied to the channel formation region of the semiconductor layer 108 to reduce oxygen vacancies in the semiconductor layer 108.

As the insulating layer 103 provided under the insulating layer 104 (on the substrate 102 side), an insulating film through which oxygen and hydrogen are less likely to be diffused is preferably used. It is particularly preferable to use a metal oxide film such as an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film.

An aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, and the like have an extremely high barrier property even when its thickness is small. Accordingly, the thickness can be greater than or equal to 0.5 nm and less than or equal to 50 nm, preferably greater than or equal to 1 nm and less than or equal to 40 nm, further preferably greater than or equal to 2 nm and less than or equal to 30 nm. In particular, an aluminum oxide film has a high barrier property against hydrogen or the like and thus gives a sufficient effect even when having an extremely small thickness (e.g., greater than or equal to 0.5 nm and less than or equal to 1.5 nm). Such a film can be formed by a deposition method such as a sputtering method or an atomic layer deposition (ALD) method.

Here, the semiconductor layer 108 and the insulating layer 104 are processed into island shapes. In FIG. 1(A), the outline of the insulating layer 104 is denoted by a dashed line. The insulating layer 104 is provided to cover at least the semiconductor layer 108 in a plan view. In other words, an end portion of the insulating layer 104 is processed to be positioned outside a region overlapping with the semiconductor layer 108. Note that the semiconductor layer 108 and the insulating layer 104 may be processed using the same etching mask as described later; in that case, the semiconductor layer 108 and the insulating layer 104 have substantially the same top surface shape.

In addition, as illustrated in FIGS. 1(B) and 1(C), the insulating layer 103 and the insulating layer 116 are provided in contact with each other in the region outside the end portion of the insulating layer 104. Thus, the semiconductor layer 108, the insulating layer 104, and the like can be sealed with the insulating layer 103 and the insulating layer 116. Such a structure can effectively inhibit diffusion of hydrogen from the outside into the semiconductor layer 108 and the insulating layer 104 of the transistor 100 and diffusion of oxygen in the semiconductor layer 108 and the insulating layer 104 into the outside.

Although the insulating layer 118 contains hydrogen in some cases, the insulating layer 104 and the insulating layer 110, each of which includes an oxide film and is in contact with the semiconductor layer 108, are not in contact with the insulating layer 118 owing to the insulating layer 116. Thus, even when the insulating layer 118 contains hydrogen, it is possible to effectively prevent diffusion of the hydrogen into the semiconductor layer 108 through the insulating layer 104 and the insulating layer 110 due to heat applied during the manufacturing process of the transistor 100 or the like.

Here, the semiconductor layer 108 and oxygen vacancies that might be formed in the semiconductor layer 108 will be described.

Oxygen vacancies formed in the semiconductor layer 108 adversely affect the transistor characteristics and therefore cause a problem. For example, when an oxygen vacancy is formed in the semiconductor layer 108, the oxygen vacancy might be bonded with hydrogen to serve as a carrier supply source. The carrier supply source generated in the semiconductor layer 108 causes a change in the electrical characteristics, typically, a shift in the threshold voltage, of the transistor 100. Therefore, it is preferable that the amount of oxygen vacancies in the semiconductor layer 108 be as small as possible.

In view of this, in one embodiment of the present invention, the insulating films near the semiconductor layer 108, specifically, the insulating layer 110 positioned over the semiconductor layer 108 and the insulating layer 104 positioned under the semiconductor layer 108 each include an oxide film. When oxygen is moved from the insulating layer 104 and the insulating layer 110 to the semiconductor layer 108 by heat applied during the manufacturing process or the like, oxygen vacancies in the semiconductor layer 108 can be reduced.

Furthermore, the semiconductor layer 108 preferably includes a region where the atomic proportion of In is higher than the atomic proportion of M. A higher atomic proportion of In results in higher field-effect mobility of the transistor.

Here, in the case of a metal oxide containing In, Ga, and Zn, bonding strength between In and oxygen is weaker than bonding strength between Ga and oxygen; hence, with a higher atomic proportion of In, oxygen vacancies tend to be generated in the metal oxide film. There is a similar tendency when a metal element shown above as M is used instead of Ga. The existence of a large amount of oxygen vacancies in the metal oxide film leads to deterioration of electrical characteristics and reduction in reliability of a transistor.

In contrast, in one embodiment of the present invention, an extremely large amount of oxygen can be supplied to the semiconductor layer 108 containing a metal oxide; thus, a metal oxide material with a high atomic proportion of In can be used. Accordingly, it is possible to achieve a transistor with extremely high field-effect mobility, stable electrical characteristics, and high reliability.

For example, a metal oxide in which the atomic proportion of In is 1.5 times or more, 2 times or more, 3 times or more, 3.5 times or more, or 4 times or more the atomic proportion of M can be favorably used.

It is particularly preferable that the atomic ratio of In, M, and Zn in the semiconductor layer 108 be In:M:Zn=5:1:6 or in the neighborhood thereof (M be greater than or equal to 0.5 and less than or equal to 1.5 and Zn be greater than or equal to 5 and less than or equal to 7 when In is 5). Alternatively, the atomic ratio of In, M, and Zn is preferably In:M:Zn=4:2:3 or in the neighborhood thereof. Furthermore, as the composition of the semiconductor layer 108, the atomic proportions of In, M, and Zn in the semiconductor layer 108 may be approximately equal to each other. That is, a material in which an atomic ratio of In, M, and Zn is In:M:Zn=1:1:1 or in the neighborhood thereof may be included.

For example, with the use of the transistor with high field-effect mobility in a gate driver that generates a gate signal, a display device with a small frame width (also referred to as a narrow frame) can be provided. Furthermore, with the use of the above transistor with high field-effect mobility in a source driver (particularly a demultiplexer connected to an output terminal of a shift register included in the source driver), a display device to which fewer wirings are connected can be provided.

Note that even when the semiconductor layer 108 includes the region where the atomic proportion of In is higher than the atomic proportion of M, the field-effect mobility may sometimes be low if the semiconductor layer 108 has high crystallinity. The crystallinity of the semiconductor layer 108 can be analyzed by using X-ray diffraction (XRD) or a transmission electron microscope (TEM), for example.

Here, impurities such as hydrogen or moisture entering the semiconductor layer 108 adversely affect the transistor characteristics and therefore cause a problem. Thus, it is preferable that the amount of impurities such as hydrogen or moisture in the semiconductor layer 108 be as small as possible. It is preferable to use a metal oxide film in which the impurity concentration is low and the density of defect states is low, in which case a transistor having excellent electrical characteristics can be fabricated. By reducing the impurity concentration and reducing the density of defect states (reducing oxygen vacancies), the carrier density in the film can be reduced. A transistor including such a metal oxide film as a semiconductor layer rarely has electrical characteristics with a negative threshold voltage (also referred to as normally-on). Furthermore, a transistor including such a metal oxide film can have characteristics of an extremely low off-state current.

The semiconductor layer 108 may have a stacked structure including two or more layers.

For example, the semiconductor layer 108 in which two or more metal oxide films with different compositions are stacked can be used. For instance, in the case of using an In—Ga—Zn oxide, it is preferable to use a stack of two or more films each formed using a sputtering target with an atomic ratio of In:M:Zn=5:1:6, In:M:Zn=4:2:3, In:M:Zn=1:1:1, In:M:Zn=2:2:1, In:M:Zn=1:3:4, or In:M:Zn=1:3:2 or in the neighborhood thereof.

Alternatively, the semiconductor layer 108 in which two or more metal oxide films with different crystallinities are stacked can be used. In this case, the metal oxide films are preferably successively formed without exposure to the atmospheric air using the same oxide target under different deposition conditions.

For example, the oxygen flow rate ratio at the time of depositing the earlier-formed first metal oxide film is set smaller than the oxygen flow rate ratio at the time of depositing the subsequently formed second metal oxide film. Alternatively, a condition without oxygen flowing is employed at the time of depositing the first metal oxide film. In such a manner, oxygen can be effectively supplied at the time of depositing the second metal oxide film. The first metal oxide film can have lower crystallinity and higher electrical conductivity than the second metal oxide film. Meanwhile, owing to the second metal oxide film as the upper film having higher crystallinity than the first metal oxide film, damage caused at the time of processing the semiconductor layer 108 or depositing the insulating layer 110 can be inhibited.

Specifically, the oxygen flow rate ratio at the time of depositing the first metal oxide film is higher than or equal to 0% and lower than 50%, preferably higher than or equal to 0% and lower than or equal to 30%, further preferably higher than or equal to 0% and lower than or equal to 20%, typically 10%. The oxygen flow rate ratio at the time of depositing the second metal oxide film is higher than or equal to 50% and lower than or equal to 100%, preferably higher than or equal to 60% and lower than or equal to 100%, further preferably higher than or equal to 80% and lower than or equal to 100%, still further preferably higher than or equal to 90% and lower than or equal to 100%, typically 100%. Although the conditions at the time of the deposition such as pressure, temperature, and power may vary between the first metal oxide film and the second metal oxide film, it is preferable to employ the same conditions other than the oxygen flow rate ratio, in which case the time required for the deposition steps can be shortened.

With such a structure, the transistor 100 with excellent electrical characteristics and high reliability can be obtained.

The above is the description of Structure example 1.

Variation Example 1

Variation examples of above Structure example 1 will be described below.

Variation Example 1-1

FIGS. 2(A) and 2(B) show an example in which the insulating layer 104 and the semiconductor layer 108 are processed into island shapes using the same etching mask. In other words, the insulating layer 104 and the semiconductor layer 108 have substantially the same top surface shape in a plan view. Furthermore, it can also be said that side surfaces of end portions of the insulating layer 104 and the semiconductor layer 108 are continuous.

With such a structure, a step for processing the insulating layer 104 can be omitted, resulting in improved yield and reduced manufacturing costs.

Variation Example 1-2

FIG. 2(C) shows an example in which the insulating layer 104 is processed such that the end portion of the insulating layer 104 is outside the semiconductor layer 108 and is positioned on an inner side than end portions of the conductive layer 112, the metal oxide layer 114, and the insulating layer 110. FIG. 2(C) illustrates a cross section in the channel width direction.

The area of the insulating layer 104 of Variation example 1-1 and Variation example 1-2 can be smaller than that of Structure example 1 described above. By changing the pattern and the formation method of the insulating layer 104 in such a manner, the amount of oxygen supplied from the insulating layer 104 to the semiconductor layer 108 can be optimized.

The above is the description of Variation example 1.

Structure Example 2

A structure example of a transistor whose structure is partly different from that of Structure example 1 described above will be described below. Note that description of the same portions as those in Structure example 1 described above is omitted below in some cases. Furthermore, in the drawings that are referred to later, the same hatching pattern is applied to portions having functions similar to those in the structure example described above, and the portions are not denoted by reference numerals in some cases.

FIG. 3(A) is a top view of a transistor 100A, FIG. 3(B) is a cross-sectional view of the transistor 100A in the channel length direction, and FIG. 3(C) is a cross-sectional view of the transistor 100A in the channel width direction.

The transistor 100A is different from Structure example 1 chiefly in including a conductive layer 106 between the substrate 102 and the insulating layer 103. The conductive layer 106 has a region overlapping with the semiconductor layer 108 and the conductive layer 112 with the insulating layer 104 and the insulating layer 103 therebetween.

In the transistor 100A, the conductive layer 106 has a function of a first gate electrode (also referred to as a bottom gate electrode), and the conductive layer 112 has a function of a second gate electrode (also referred to as a top gate electrode). Part of the insulating layer 103 and part of the insulating layer 104 function as a first gate insulating layer, and part of the insulating layer 110 functions as a second gate insulating layer.

A portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. Note that for easy explanation, a portion of the semiconductor layer 108 that overlaps with the conductive layer 112 will be sometimes referred to as a channel formation region in the following description; however, a channel can be actually formed in a portion not overlapping with the conductive layer 112 and overlapping with the conductive layer 106 (a portion including the region 108 n).

As illustrated in FIG. 3(C), the conductive layer 106 may be electrically connected to the conductive layer 112 through an opening portion 142 provided in the metal oxide layer 114, the insulating layer 110, the insulating layer 104, and the insulating layer 103. Thus, the same potential can be supplied to the conductive layer 106 and the conductive layer 112.

For the conductive layer 106, a material similar to that for the conductive layer 112, the conductive layer 120 a, or the conductive layer 120 b can be used. It is particularly favorable to form the conductive layer 106 using a material containing copper because the resistance can be reduced.

As illustrated in FIGS. 3(A) and 3(C), the conductive layer 112 and the conductive layer 106 preferably extend beyond an end portion of the semiconductor layer 108 in the channel width direction. In that case, as illustrated in FIG. 3(C), the semiconductor layer 108 is entirely covered with the conductive layer 112 and the conductive layer 106 in the channel width direction with the insulating layer 110 and the insulating layer 104 therebetween.

With such a structure, the semiconductor layer 108 can be electrically surrounded by electric fields generated by a pair of gate electrodes. At this time, it is particularly preferable that the same potential be supplied to the conductive layer 106 and the conductive layer 112. In that case, electric fields for inducing a channel can be effectively applied to the semiconductor layer 108, whereby the on-state current of the transistor 100A can be increased. Thus, the transistor 100A can also be miniaturized.

Note that a structure in which the conductive layer 112 and the conductive layer 106 are not connected to each other may be employed. In that case, a constant potential may be supplied to one of the pair of gate electrodes, and a signal for driving the transistor 100A may be supplied to the other. In this case, the potential supplied to one of the electrodes can control the threshold voltage at the time of driving the transistor 100A with the other electrode.

The above is the description of Structure example 2.

Variation Example 2

Variation examples of above Structure example 2 will be described below.

Variation Example 2-1

FIGS. 4(A) and 4(B) show an example in which the insulating layer 104 and the semiconductor layer 108 are processed into island shapes using the same etching mask.

Here, as illustrated in FIG. 4(B), the conductive layer 112 and the conductive layer 106 are electrically connected to each other through the opening portion 142 provided in the metal oxide layer 114, the insulating layer 110, and the insulating layer 103.

Variation Example 2-2

FIG. 5(A) shows an example in which the insulating layer 104 is processed such that the end portion of the insulating layer 104 is outside the semiconductor layer 108, the conductive layer 112, the metal oxide layer 114, and the insulating layer 110 and is positioned on an inner side than the conductive layer 106.

Variation Example 2-3

FIGS. 5(B) and 5(C) each show an example in which the end portion of the insulating layer 104 is outside the semiconductor layer 108 and is positioned on an inner side than the conductive layer 112, the metal oxide layer 114, the insulating layer 110, and the conductive layer 106.

FIG. 5(B) shows an example in which the opening portion 142 is provided in a position where the insulating layer 104 does not exist. FIG. 5(C) shows an example in which the opening portion 142 is provided in a position where the insulating layer 104 exists.

In the structures illustrated in FIG. 4(B) (Variation example 2-1) and FIGS. 5(B) and 5(C) (Variation example 2-3), part of the conductive layer 112 that is outside the end portion of the insulating layer 104 is positioned under the semiconductor layer 108 in the channel width direction of the transistor. With such a structure, the semiconductor layer 108 can be electrically surrounded by the electric fields generated by the pair of gate electrodes more effectively, so that the on-state current of the transistor can be increased.

The above is the description of Variation example 2.

Application Examples

Examples of a case where the above-described transistor is applied to a pixel of a display device are described below.

FIG. 6(A) is a schematic top view of a display device in which a plurality of subpixels are arranged in a matrix. One subpixel includes at least the transistor 100 and a conductive layer 131 that is electrically connected to the transistor 100 and functions as a pixel electrode. Although a simplified structure of the subpixel is illustrated here, another transistor, a capacitor, or the like can be provided as appropriate depending on a display element applied to the subpixel.

In FIG. 6(A), the conductive layer 112 functions as a gate line (also referred to as a scan line), the conductive layer 120 a functions as a source line (also referred to as a signal line or a video signal line), and the conductive layer 120 b functions as a wiring that electrically connects the transistor 100 and the conductive layer 131.

FIG. 6(A) shows an example in which one island-shaped insulating layer 104 is provided for one transistor. It can also be said that one insulating layer 104 overlaps with one semiconductor layer 108.

FIGS. 6(B) and 6(C) each show a structure example in which one insulating layer 104 overlaps with two or more semiconductor layers 108.

FIG. 6(B) illustrates a portion including both ends of the gate line (the conductive layer 112) in the extending direction in a display region 130 of the display device. In FIG. 6(B), the insulating layer 104 is processed to get across the display region 130.

FIG. 6(C) illustrates a portion including the entire display region 130 of the display device. In FIG. 6(C), one insulating layer 104 is processed to be provided to cover the entire display region 130. In other words, the insulating layer 104 is provided to overlap with all of the semiconductor layers 108 provided in the display region 130.

As illustrated in FIGS. 6(B) and 6(C), when the insulating layer 104 is used in common by two or more subpixels, high definition can be easily achieved.

Note that the structure of the insulating layer 104 is not limited to the above, and one insulating layer 104 may be provided for every pixel or every block including several pixels. In the case where one subpixel includes a plurality of transistors, one insulating layer may be provided for one subpixel.

The transistor of one embodiment of the present invention can be applied to not only a display device but also a variety of circuits and devices. For example, the transistor of one embodiment of the present invention can be favorably used for a variety of circuits such as an arithmetic circuit, a memory circuit, a driver circuit, and an interface circuit in an IC chip mounted on an electronic device or the like, a driver circuit in a display device including a liquid crystal element, an organic EL element, or the like or a variety of sensor devices, or the like.

In this case, for example, one insulating layer 104 is provided to cover a block including one or more transistors 100 (e.g., per circuit or per chip) and a region where the insulating layer 116 and the insulating layer 103 are in contact with each other is provided around the insulating layer 104, whereby a plurality of transistors 100 in the block can be sealed with the insulating layer 103 and the insulating layer 116. Accordingly, diffusion of hydrogen from the outside into the semiconductor layer 108 of the transistor 100 and diffusion of oxygen in the semiconductor layer 108 into the outside are effectively inhibited, so that a highly reliable device can be achieved.

The above is the description of the application example.

Components of Semiconductor Device

Next, components of the semiconductor device in this embodiment will be described in detail.

Substrate

Although there is no particular limitation on a material and the like of the substrate 102, it is necessary that the substrate have heat resistance high enough to withstand at least heat treatment performed later. For example, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate including silicon or silicon carbide as a material, a compound semiconductor substrate of silicon germanium or the like, an SOT substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. Alternatively, any of these substrates over which a semiconductor element is provided may be used as the substrate 102.

A flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor 100 and the like. The separation layer can be used when part or the whole of a semiconductor device completed thereover is separated from the substrate 102 and transferred onto another substrate. In such a case, the transistor 100 and the like can be transferred onto a substrate having low heat resistance or a flexible substrate as well.

Insulating Layer 104

The insulating layer 104 can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, or the like as appropriate. For example, the insulating layer 104 can be formed of a single layer or a stacked layer of an oxide insulating film or a nitride insulating film. To improve the properties of the interface with the semiconductor layer 108, at least a region in the insulating layer 104, which is in contact with the semiconductor layer 108, is preferably formed of an oxide insulating film. An oxide insulating film from which oxygen is released by heating is preferably used as the insulating layer 104.

For example, a single layer or a stacked layer using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, a Ga—Zn oxide, or the like can be provided as the insulating layer 104.

In the case where a film other than an oxide film, such as a silicon nitride film, is used for the side of the insulating layer 104 that is in contact with the semiconductor layer 108, pretreatment such as oxygen plasma treatment is preferably performed on a surface in contact with the semiconductor layer 108 to oxidize the surface or the vicinity of the surface.

Conductive Film

The conductive layer 112 and the conductive layer 106 that function as the gate electrode, the conductive layer 120 a that functions as one of the source electrode and the drain electrode, and the conductive layer 120 b that functions as the other of the source electrode and the drain electrode can each be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt; an alloy containing any of these metal elements as its component; an alloy including a combination of any of these metal elements; or the like.

For the conductive layer 112, the conductive layer 106, the conductive layer 120 a, and the conductive layer 120 b, an oxide conductor or a metal oxide film such as an In—Sn oxide, an In—W oxide, an In—W—Zn oxide, an In—Ti oxide, an In—Ti—Sn oxide, an In—Zn oxide, an In—Sn—Si oxide, or an In—Ga—Zn oxide can also be used.

Here, an oxide conductor (OC) is described. For example, oxygen vacancies are formed in a metal oxide having semiconductor characteristics, and then hydrogen is added to the oxygen vacancies, so that a donor level is formed in the vicinity of the conduction band. As a result, the conductivity of the metal oxide is increased, so that the metal oxide becomes a conductor. The metal oxide having become a conductor can be referred to as an oxide conductor.

The conductive layer 112 or the like may have a stacked-layer structure of a conductive film containing the above-described oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. The use of the conductive film containing a metal or an alloy can reduce the wiring resistance. At this time, a conductive film containing an oxide conductor is preferably used as the conductive film in contact with the insulating layer functioning as a gate insulating film.

Among the above-mentioned metal elements, it is particularly preferable that any one or more metal elements selected from titanium, tungsten, tantalum, and molybdenum be included in the conductive layer 112, the conductive layer 106, the conductive layer 120 a, and the conductive layer 120 b. It is particularly preferable that a tantalum nitride film be used. Since the tantalum nitride film has conductivity and a high barrier property against copper, oxygen, or hydrogen and releases little hydrogen from itself, it can be favorably used as the conductive film in contact with the semiconductor layer 108 or the conductive film in the vicinity of the semiconductor layer 108.

Insulating Layer 110

The insulating layer 110 functioning as a gate insulating film of the transistor 100 or the like can be formed by a PECVD method, a sputtering method, or the like. As the insulating layer 110, an insulating layer including one or more of the following films can be used: a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. Note that the insulating layer 110 may have a stacked-layer structure of two layers or a stacked-layer structure of three or more layers.

The insulating layer 110 that is in contact with the semiconductor layer 108 is preferably an oxide insulating film and more preferably includes a region containing oxygen in excess of that in the stoichiometric composition. In other words, the insulating layer 110 is an insulating film capable of releasing oxygen. For example, it is also possible to supply oxygen to the insulating layer 110 by forming the insulating layer 110 in an oxygen atmosphere, performing heat treatment, plasma treatment, or the like on the deposited insulating layer 110 in an oxygen atmosphere, or depositing an oxide film over the insulating layer 110 in an oxygen atmosphere.

For the insulating layer 110, a material having a larger dielectric constant than silicon oxide or silicon oxynitride, such as hafnium oxide, can also be used. In that case, the insulating layer 110 can be thick and leakage current due to tunnel current can be inhibited. Specifically, hafnium oxide having crystallinity is preferable because it has a higher dielectric constant than amorphous hafnium oxide.

Semiconductor Layer

In the case where the semiconductor layer 108 is an In—M—Zn oxide, a sputtering target used for depositing the In-M-Zn oxide preferably has the atomic proportion of In higher than or equal to the atomic proportion of M. Examples of the atomic ratio of the metal elements in such a sputtering target includes In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, and the like.

A target containing a polycrystalline oxide is preferably used as the sputtering target, which facilitates formation of the semiconductor layer 108 having crystallinity. Note that the atomic ratio in the semiconductor layer 108 to be deposited varies in the range of ±40% from any of the above atomic ratios of the metal elements contained in the sputtering target. For example, in the case where the composition of a sputtering target used for the semiconductor layer 108 is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the semiconductor layer 108 to be deposited is in the neighborhood of In:Ga:Zn=4:2:3 [atomic ratio] in some cases.

Note that when the atomic ratio is described as In:Ga:Zn=4:2:3 or in the neighborhood thereof, the case is included where the atomic proportion of Ga is greater than or equal to 1 and less than or equal to 3 and the atomic proportion of Zn is greater than or equal to 2 and less than or equal to 4 with the atomic proportion of In being 4. When the atomic ratio is described as In:Ga:Zn=5:1:6 or in the neighborhood thereof, the case is included where the atomic proportion of Ga is greater than 0.1 and less than or equal to 2 and the atomic proportion of Zn is greater than or equal to 5 and less than or equal to 7 with the atomic proportion of In being 5. When the atomic ratio is described as In:Ga:Zn=1:1:1 or in the neighborhood thereof, the case is included where the atomic proportion of Ga is greater than 0.1 and less than or equal to 2 and the atomic proportion of Zn is greater than 0.1 and less than or equal to 2 with the atomic proportion of In being 1.

The energy gap of the semiconductor layer 108 is 2 eV or more, preferably 2.5 eV or more. With the use of such a metal oxide having a wider energy gap than silicon, the off-state current of the transistor can be reduced.

Furthermore, the semiconductor layer 108 preferably has a non-single-crystal structure. The non-single-crystal structure includes, for example, a CAAC structure which will be described later, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single-crystal structures, the amorphous structure has the highest density of defect states, whereas the CAAC structure has the lowest density of defect states.

A CAAC (c-axis aligned crystal) will be described below. A CAAC refers to an example of a crystal structure.

Note that the CAAC structure is a crystal structure of a thin film or the like that has a plurality of nanocrystals (crystal regions having a maximum diameter of less than 10 nm), characterized in that the nanocrystals have c-axis alignment in a particular direction and are not aligned but continuously connected in the a-axis and b-axis directions without forming a grain boundary. In particular, a thin film having the CAAC structure is characterized in that the c-axes of nanocrystals are likely to be aligned in the film thickness direction, the normal direction of the surface where the thin film is formed, or the normal direction of the surface of the thin film.

A CAAC-OS (Oxide Semiconductor) is an oxide semiconductor with high crystallinity. On the other hand, a clear crystal grain boundary cannot be observed in the CAAC-OS; thus, it can be said that a reduction in electron mobility due to the crystal grain boundary is less likely to occur. Furthermore, entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor, which means that the CAAC-OS is an oxide semiconductor having small amounts of impurities and defects (e.g., oxygen vacancies). Thus, an oxide semiconductor including a CAAC-OS is physically stable. Therefore, the oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.

Here, in crystallography, a unit cell is formed with three axes (crystal axes) of the a-axis, the b-axis, and the c-axis; in general, a specific axis is taken as the c-axis in the unit cell. In particular, in the case of a crystal having a layered structure, two axes parallel to the plane direction of a layer are regarded as the a-axis and the b-axis and an axis intersecting with the layer is regarded as the c-axis in general. Typical examples of such a crystal having a layered structure include graphite, which is classified as a hexagonal system. In a unit cell of graphite, the a-axis and the b-axis are parallel to the cleavage plane and the c-axis is orthogonal to the cleavage plane. For example, an InGaZnO₄ crystal having a YbFe₂O₄ type crystal structure which is a layered structure can be classified as a hexagonal system, and in a unit cell thereof, the a-axis and the b-axis are parallel to the plane direction of the layer and the c-axis is orthogonal to the layer (i.e., the a-axis and the b-axis).

An example of a crystal structure of a metal oxide is described. Note that a metal oxide deposited by a sputtering method using an In—Ga—Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) is described below as an example. A metal oxide that is formed by a sputtering method using the above-described target at a substrate temperature higher than or equal to 100° C. and lower than or equal to 130° C. is likely to have either the nc (nano crystal) structure or the CAAC structure, or a structure in which both structures are mixed. In contrast, a metal oxide formed by a sputtering method at a substrate temperature set at room temperature (R.T.) is likely to have the nc structure. Note that room temperature (R.T.) here also includes a temperature in the case where a substrate is not heated intentionally.

Manufacturing Method Example

A manufacturing method example of a transistor of one embodiment of the present invention will be described below. Here, description will be made giving, as an example, the transistor 100A described in Structure example 2.

Note that thin films that form the semiconductor device (insulating films, semiconductor films, conductive films, and the like) can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulse laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like. Examples of the CVD method include a plasma-enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. In addition, as an example of the thermal CVD method, a metal organic CVD (MOCVD) method can be given.

The thin films that form the semiconductor device (insulating films, semiconductor films, conductive films, and the like) can be formed by a method such as spin coating, dipping, spray coating, ink-jetting, dispensing, screen printing, offset printing, a doctor knife, slit coating, roll coating, curtain coating, or knife coating.

When the thin films that form the semiconductor device are processed, a photolithography method or the like can be used for the processing. Besides, a nanoimprinting method, a sandblasting method, a lift-off method, or the like may be used for the processing of the thin films. Island-shaped thin films may be directly formed by a deposition method using a blocking mask such as a metal mask.

There are the following two typical ways of a photolithography method. One is a method in which a resist mask is formed over a thin film that is to be processed, the thin film is processed by etching or the like, and the resist mask is removed. The other is a method in which, after a photosensitive thin film is deposited, exposure and development are performed to process the thin film into a desired shape.

As light used for exposure in a photolithography method, for example, an i-line (with a wavelength of 365 nm), a g-line (with a wavelength of 436 nm), an h-line (with a wavelength of 405 nm), or combined light of any of them can be used. Besides, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Furthermore, exposure may be performed by liquid immersion light exposure technique. Furthermore, as the light used for the exposure, extreme ultra-violet (EUV) light or X-rays may be used. Furthermore, instead of the light used for the exposure, an electron beam can also be used. It is preferable to use extreme ultra-violet light, X-rays, or an electron beam because extremely minute processing can be performed. Note that in the case of performing exposure by scanning of a beam such as an electron beam, a photomask is unnecessary.

For etching of thin films, a dry etching method, a wet etching method, a sandblast method, or the like can be used.

In each of drawings shown in FIG. 7 to FIG. 9, cross sections of the transistor 100A in the channel length direction and in the channel width direction in each step in the manufacturing process are shown side by side.

Formation of Conductive Layer 106

A conductive film is deposited over the substrate 102 and processed by etching, whereby the conductive layer 106 functioning as a gate electrode is formed (FIG. 7(A)).

Formation of Insulating Layer 103 and Insulating Layer 104

Then, to cover the substrate 102 and the conductive layer 106, the insulating layer 103 and the insulating layer 104 are formed to be stacked (FIG. 7(B)). The insulating layer 103 and the insulating layer 104 can be formed by a PECVD method, an ALD method, a sputtering method, or the like.

For example, the insulating layer 103 can be formed by an ALD method or a sputtering method, and the insulating layer 104 can be formed by a PECVD method or a sputtering method.

Next, part of the insulating layer 104 is removed by etching, so that the insulating layer 104 is processed into an island shape (FIG. 7(C)).

Formation of Semiconductor Layer 108

Next, a metal oxide film is deposited over the insulating layer 104 and the insulating layer 103 and processed to form the semiconductor layer 108.

The metal oxide film is preferably formed by a sputtering method using a metal oxide target.

In depositing the metal oxide film, an inert gas (e.g., a helium gas, an argon gas, or a xenon gas) may be mixed in addition to the oxygen gas. Note that when the proportion of an oxygen gas in the whole deposition gas (hereinafter also referred to as an oxygen flow rate ratio) at the time of depositing the metal oxide film is higher, the crystallinity of the metal oxide film can be higher and a transistor with higher reliability can be obtained. On the other hand, when the oxygen flow rate ratio is lower, the crystallinity of the metal oxide film is lower and a transistor with a high on-state current can be obtained.

As deposition conditions of the metal oxide film, the substrate temperature is preferably set to higher than or equal to room temperature and lower than 200° C., preferably higher than or equal to room temperature and lower than or equal to 140° C. For example, when the deposition temperature is higher than or equal to room temperature and lower than 140° C., high productivity is achieved, which is preferable. When the metal oxide film is deposited with the substrate temperature set at room temperature or without intentional heating, the crystallinity can be made low.

Before deposition of the metal oxide film, it is preferable to perform treatment for desorbing water, hydrogen, an organic substance, or the like adsorbed onto a surface of the insulating layer 104 or treatment for supplying oxygen into the insulating layer 104. For example, heat treatment can be performed at a temperature higher than or equal to 70° C. and lower than or equal to 200° C. in a reduced-pressure atmosphere. Alternatively, plasma treatment may be performed in an oxygen-containing atmosphere. When plasma treatment is performed in an N₂O gas-containing atmosphere, an organic substance on the surface of the insulating layer 104 can be favorably removed. After such treatment, the metal oxide film is preferably deposited successively without exposure of the surface of the insulating layer 104 to the atmospheric air.

For processing of the metal oxide film, one or both of a wet etching method and a dry etching method can be used. At this time, part of the insulating layer 104 that does not overlap with the semiconductor layer 108 is etched and thinned in some cases.

After the metal oxide film is deposited or processed into the semiconductor layer 108, heat treatment may be performed to remove hydrogen or water in the metal oxide film or the semiconductor layer 108. The temperature of the heat treatment is typically higher than or equal to 150° C. and lower than the strain point of the substrate, higher than or equal to 250° C. and lower than or equal to 450° C., or higher than or equal to 300° C. and lower than or equal to 450° C.

The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, heating may be performed in the atmosphere, and then heating may be performed in an oxygen-containing atmosphere. It is preferable that the atmosphere of the above heat treatment do not contain hydrogen, water, or the like. An electric furnace, an RTA (Rapid Thermal Anneal) apparatus, or the like can be used for the heat treatment. The use of the RTA apparatus can shorten the heat treatment time.

Formation of Insulating Film 110 f and Metal Oxide Film 114 f

Next, to cover the insulating layer 103, the insulating layer 104, and the semiconductor layer 108, an insulating film 110 f to be the insulating layer 110 and a metal oxide film 114 f to be the metal oxide layer 114 are deposited to be stacked.

As the insulating film 110 f, for example, an oxide film such as a silicon oxide film or a silicon oxynitride film is preferably formed with a plasma-enhanced chemical vapor deposition apparatus (a PECVD apparatus or simply referred to as a plasma CVD apparatus). Alternatively, the insulating film 110 f may be formed by a PECVD method using a microwave.

The metal oxide film 114 f is preferably deposited in an oxygen-containing atmosphere, for example. It is particularly preferable that the metal oxide film 114 f be deposited by a sputtering method in an oxygen-containing atmosphere. In that case, oxygen can be supplied to the insulating film 110 f at the time of the deposition of the metal oxide film 114 f.

For example, the metal oxide film 114 f is preferably deposited by a reactive sputtering method with a metal target using oxygen as a deposition gas. When aluminum is used for the metal target, for example, an aluminum oxide film can be deposited.

At the time of depositing the metal oxide film 114 f, a larger amount of oxygen can be supplied to the insulating film 110 f with a higher proportion of the oxygen flow rate to the total flow rate of the deposition gas introduced into a deposition chamber of a deposition apparatus (a higher oxygen flow rate ratio), or with a higher oxygen partial pressure in the deposition chamber. The oxygen flow rate ratio or the oxygen partial pressure is, for example, higher than or equal to 50% and lower than or equal to 100%, preferably higher than or equal to 65% and lower than or equal to 100%, further preferably higher than or equal to 80% and lower than or equal to 100%, still further preferably higher than or equal to 90% and lower than or equal to 100%. It is particularly preferable that the oxygen flow rate ratio be 100% and the oxygen partial pressure be as close to 100% as possible.

When the metal oxide film 114 f is formed by a sputtering method in an oxygen-containing atmosphere in the above manner, oxygen can be supplied to the insulating film 110 f and release of oxygen from the insulating film 110 f can be prevented during the deposition of the metal oxide film 114 f. As a result, an extremely large amount of oxygen can be enclosed in the insulating film 110 f. Moreover, a large amount of oxygen can be supplied to the semiconductor layer 108 by heat treatment performed later. Thus, oxygen vacancies in the semiconductor layer 108 can be reduced, leading to a highly reliable transistor.

Then, after the deposition of the metal oxide film 114 f, the metal oxide film 114 f, the insulating film 110 f, the insulating layer 104, and the insulating layer 103 are partly removed by etching to form an opening reaching the conductive layer 106. Accordingly, the conductive layer 112 to be formed later can be electrically connected to the conductive layer 106 through the opening.

A schematic cross-sectional view at this stage corresponds to FIG. 8(B).

Formation of Conductive Layer 112, Metal Oxide Layer 114, and the Insulating Layer 110

Subsequently, a conductive film to be the conductive layer 112 is deposited over the metal oxide film 114 f The conductive film is preferably deposited by a sputtering method using a sputtering target of a metal or an alloy.

Next, the conductive film, the metal oxide film 114 f, and the insulating film 110 f are partly etched (FIG. 8(C)). The conductive film, the metal oxide film 114 f, and the insulating film 110 f are preferably processed using the same resist mask. Alternatively, the conductive layer 112 after etching may be used as a hard mask for etching of the metal oxide film 114 f and the insulating film 110 f.

In such a manner, the island-shaped conductive layer 112, metal oxide layer 114, and insulating layer 110 that have substantially the same top surface shape can be formed.

Note that during etching of the metal oxide film 114 f and the insulating film 110 f, the semiconductor layer 108 that is not covered with the insulating layer 110 may sometimes be etched and reduced in thickness.

Formation of Insulating Layer 116

Next, the insulating layer 116 is formed to cover the insulating layer 104, the semiconductor layer 108, the side surface of the insulating layer 110, the side surface of the metal oxide layer 114, the conductive layer 112, and the like. At this time, a region where the insulating layer 103 and the insulating layer 116 are in contact with each other is formed outside the end portion of the insulating layer 104 (FIG. 9(A)).

It is preferable to form the insulating layer 116 by a reactive sputtering method using a sputtering target containing the above-described metal element and, as a deposition gas, a mixed gas of a nitrogen gas and a rare gas or the like that is a dilution gas. Thus, the film quality of the insulating layer 116 can be easily controlled by controlling the flow rate ratio of the deposition gas.

For example, in the case where an aluminum nitride film formed by a reactive sputtering method using an aluminum target is used as the insulating layer 116, the flow rate of a nitrogen gas to the total flow rate of the deposition gas is preferably higher than or equal to 30% and lower than or equal to 100%, further preferably higher than or equal to 40% and lower than or equal to 100%, still further preferably higher than or equal to 50% and lower than or equal to 100%.

At the time when the insulating layer 116 is deposited, the low-resistance region 108 n is formed at the interface of the semiconductor layer 108 that is in contact with the insulating layer 116 and in a region in the vicinity of the interface.

First Heat Treatment

Sequentially, heat treatment is preferably performed. By the heat treatment, the reduction in the resistance of the region 108 n of the semiconductor layer 108 can be further promoted.

The heat treatment is preferably performed in an inert gas atmosphere such as nitrogen or a rare gas. The temperature of the heat treatment is preferably as high as possible and can be set in consideration of the heat resistance of the substrate 102, the conductive layer 106, the conductive layer 112, and the like. The temperature can be set higher than or equal to 120° C. and lower than or equal to 500° C., preferably higher than or equal to 150° C. and lower than or equal to 450° C., further preferably higher than or equal to 200° C. and lower than or equal to 400° C., still further preferably higher than or equal to 250° C. and lower than or equal to 400° C., for example. When the temperature of the heat treatment is approximately 350° C., for example, the semiconductor device can be manufactured at a high yield with production facilities using a large-size glass substrate.

Note that the heat treatment may be performed in any step after the formation of the insulating layer 116. In addition, this heat treatment may double as another heat treatment.

By the heat treatment, for example, oxygen in the semiconductor layer 108 is extracted to the insulating layer 116 side; thus, an oxygen vacancy is generated. The oxygen vacancy and hydrogen contained in the semiconductor layer 108 are combined, so that the carrier concentration is increased and the resistance of a portion that is in contact with the insulating layer 116 might be reduced.

Alternatively, when the metal element contained in the semiconductor layer 108 is diffused toward the vicinity of the interface between the semiconductor layer 108 and the insulating layer 116 by the heat treatment and a region having a high concentration of the metal element is formed, the resistance of the portion in contact with the insulating layer 116 is reduced in some cases. In the case where a metal oxide film containing indium is used as the semiconductor layer 108, a region having a high indium concentration is observed in the vicinity of the interface between the semiconductor layer 108 and the insulating layer 116 in some cases.

The region 108 n, whose resistance has been reduced because of the above complex action, becomes a highly stable low-resistance region. The region 108 n formed in the above manner is characterized in that the resistance is not easily increased again even if treatment for supplying oxygen is performed in a later step, for example.

Formation of Insulating Layer 118

Next, the insulating layer 118 is formed to cover the insulating layer 116. The insulating layer 118 can be formed, for example, by a PECVD method.

Formation of Opening Portions 141 a and 141 b

Next, the insulating layer 118 and the insulating layer 116 are partly etched, so that the opening portion 141 a and the opening portion 141 b that reach the regions 108 n are formed.

Formation of Conductive Layers 120 a and 120 b

Next, a conductive film is deposited over the insulating layer 118 so as to cover the opening portion 141 a and the opening portion 141 b, and the conductive film is processed into a desired shape, whereby the conductive layer 120 a and the conductive layer 120 b are formed (FIG. 9(B)).

Through the above process, the transistor 100A can be manufactured.

Note that in the case of employing the structures exemplified in Structure example 1 and Variation example 1, the step of forming the conductive layer 106 and the step of forming the opening portion 142 in the above manufacturing method example are omitted.

The above is the description of the manufacturing method example.

At least part of the structure examples, the manufacturing method examples, the drawings corresponding thereto, and the like exemplified in this embodiment can be implemented in combination with the other structure examples, the other manufacturing method examples, the other drawings corresponding thereto, and the like as appropriate.

At least part of this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

Embodiment 2

In this embodiment, an example of a display device that includes the transistors exemplified in the above embodiment is described.

Structure Example

FIG. 10(A) shows a top view of a display device 700. The display device 700 includes a first substrate 701 and a second substrate 705 that are bonded to each other with a sealant 712. Over the first substrate 701, a pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 are provided in the region sealed with the first substrate 701, the second substrate 705, and the sealant 712. In the pixel portion 702, a plurality of display elements are provided.

A portion of the first substrate 701 that does not overlap with the second substrate 705 is provided with an FPC terminal portion 708 to which an FPC 716 (FPC: Flexible printed circuit) is connected. The FPC 716 supplies a variety of signals to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC terminal portion 708 and a signal line 710.

A plurality of gate driver circuit portions 706 may be provided. Each of the gate driver circuit portion 706 and the source driver circuit portion 704 may be formed separately over a semiconductor substrate or the like and may be in the form of a packaged IC chip. The IC chip can be mounted over the first substrate 701 or on the FPC 716.

The transistor which is a semiconductor device of one embodiment of the present invention can be applied to transistors included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706.

Examples of the display element provided in the pixel portion 702 include a liquid crystal element and a light-emitting element. As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, a transflective liquid crystal element, or the like can be used. As the light-emitting element, a self-luminous light-emitting element such as an LED (Light Emitting Diode), an OLED (Organic LED), a QLED (Quantum-dot LED), or a semiconductor laser can be given. Moreover, a MEMS (Micro Electro Mechanical Systems) shutter element, an optical interference type MEMS element, or a display element using a microcapsule method, an electrophoretic method, an electrowetting method, an Electronic Liquid Powder (registered trademark) method, or the like can also be used, for instance.

A display device 700A illustrated in FIG. 10(B) is a display device that can be suitably used for an electronic device with a large screen. For example, the display device 700A can be suitably used for a television device, a monitor device, a personal computer (including a laptop personal computer and a desktop personal computer), a tablet terminal, digital signage, and the like.

The display device 700A includes a plurality of source driver ICs 721 and a pair of gate driver circuit portions 722.

The plurality of source driver ICs 721 are attached to respective FPCs 723. One terminal of each of the plurality of FPCs 723 is connected to the first substrate 701 and the other terminal is connected to a printed circuit board 724. When the FPCs 723 are bent, mounting on an electronic device can be performed with the printed circuit board 724 placed on the rear side of the pixel portion 702, so that the space of the electronic device can be saved.

On the other hand, the gate driver circuit portions 722 are provided over the first substrate 701. Thus, an electronic device with a narrow frame can be obtained.

With such a structure, a large-size and high-resolution display device can be obtained. For example, such a structure can also be employed for a display device whose screen diagonal is 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more. Furthermore, a display device with extremely high resolution such as full high definition, 4K2K, or 8K4K can be obtained.

Cross-Sectional Structure Example

Structures including a liquid crystal element and an EL element as display elements are described below with reference to FIG. 11 to FIG. 13. Note that FIG. 11 to FIG. 13 are cross-sectional views taken along a dashed-dotted line Q-R in FIG. 10(A). FIG. 11 and FIG. 12 each illustrate a structure including a liquid crystal element as a display element, and FIG. 13 illustrates a structure including an EL element as a display element.

Description of Common Portions in Display Devices

The display device 700 illustrated in FIG. 11 to FIG. 13 includes a lead wiring portion 711, the pixel portion 702, the source driver circuit portion 704, and the FPC terminal portion 708. The lead wiring portion 711 includes the signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752.

As the transistor 750 and the transistor 752, the transistors exemplified in Embodiment 1 can be used.

The transistor used in this embodiment includes a highly purified oxide semiconductor film in which formation of oxygen vacancies is suppressed. The transistor can have a low off-state current. Accordingly, an electrical signal such as an image signal can be held for a longer period of time, and the interval between writing operations for image signals or the like can be set longer. Accordingly, the frequency of refresh operations can be reduced, resulting in an effect of reducing power consumption.

The transistor used in this embodiment can have relatively high field-effect mobility and thus is capable of high-speed operation. For example, with the use of such a transistor capable of high-speed operation for a display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over one substrate. That is, a semiconductor device formed with a silicon wafer or the like does not need to be used separately as the driver circuit, which enables a reduction in the number of components of the display device. Moreover, the use of the transistor capable of high-speed operation in the pixel portion can provide a high-quality image.

The capacitor 790 includes a lower electrode formed in such a manner that the film which is the same as that for the semiconductor layer of the transistor 750 is processed and the resistance is reduced, and an upper electrode formed by processing the conductive film which is the same as that for a source electrode or a drain electrode. Furthermore, two insulating films covering the transistor 750 are provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked-layer structure in which the insulating films functioning as dielectric films are interposed between a pair of electrodes.

A planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.

As the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704, transistors having different structures may be used. For example, a top-gate transistor may be used as one of the transistors and a bottom-gate transistor may be used as the other. Note that the source driver circuit portion 704 described above may be replaced with a gate driver circuit portion.

The signal line 710 is formed using the conductive film which is the same as that for the source electrodes and the drain electrodes of the transistors 750 and 752, and the like. Here, a low-resistance material such as a material containing a copper element is preferably used, in which case signal delay or the like due to the wiring resistance or the like can be reduced and display on a large screen is possible.

The FPC terminal portion 708 includes a wiring 760 partly serving as a connection electrode, an anisotropic conductive film 780, and the FPC 716. The wiring 760 is electrically connected to a terminal included in the FPC 716 through the anisotropic conductive film. Here, the wiring 760 is formed using the conductive film which is the same as that for the source electrodes and the drain electrodes of the transistors 750 and 752, and the like.

As the first substrate 701 and the second substrate 705, a glass substrate or a flexible substrate such as a plastic substrate can be used, for example.

A structure body 778 between the first substrate 701 and the second substrate 705 functions as a columnar spacer that adjusts a distance (a cell gap) between the first substrate 701 and the second substrate 705. Note that the structure body 778 may be formed on the second substrate 705 side, or a spherical spacer may be used.

On the second substrate 705 side, a light-blocking film 738, a coloring film 736, and an insulating film 734 that is in contact with these films are provided.

Structure Example of Display Device Using Liquid Crystal Element

The display device 700 illustrated in FIG. 11 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776 provided therebetween. The conductive film 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive film 772 is electrically connected to the source electrode or the drain electrode included in the transistor 750. The conductive film 772 is formed over the planarization insulating film 770 and functions as a pixel electrode.

For the conductive film 772, a material having a visible-light-transmitting property or a material having a visible-light-reflective property can be used. An oxide material containing indium, zinc, tin, or the like is preferably used as the material having a light-transmitting property, for example. A material containing aluminum, silver, or the like is preferably used as the material having a reflective property, for example.

When a material having a reflective property is used for the conductive film 772, the display device 700 is a reflective liquid crystal display device. On the other hand, when a material having a light-transmitting property is used for the conductive film 772, the display device 700 is a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewer side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates are provided such that the liquid crystal element is interposed therebetween.

The display device 700 illustrated in FIG. 12 is an example in which the liquid crystal element 775 in a horizontal electric field mode (e.g., FFS mode) is used. The conductive film 774 functioning as a common electrode is provided over the conductive film 772 with an insulating film 773 interposed therebetween. The alignment state of the liquid crystal layer 776 can be controlled by the electric field generated between the conductive film 772 and the conductive film 774.

Although not illustrated in FIG. 11 and FIG. 12, an alignment film in contact with the liquid crystal layer 776 may be provided. An optical member (an optical substrate) such as a polarizing member, a retardation member, or an anti-reflection member and a light source such as a backlight or a side light can be provided as appropriate.

As the liquid crystal layer 776, thermotropic liquid crystal, low-molecular liquid crystal, high-molecular liquid crystal, polymer dispersed liquid crystal, polymer network liquid crystal, ferroelectric liquid crystal, anti-ferroelectric liquid crystal, or the like can be used. In the case of employing a horizontal electric field mode, liquid crystal exhibiting a blue phase for which an alignment film is not used may be used.

As the mode of the liquid crystal element, a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Birefringence) mode, an ECB (Electrically Controlled Birefringence) mode, a guest-host mode, or the like can be employed.

Display Device Using Light-Emitting Element

The display device 700 illustrated in FIG. 13 includes a light-emitting element 782. The light-emitting element 782 includes the conductive film 772, an EL layer 786, and a conductive film 788. The EL layer 786 contains an organic compound or an inorganic compound such as a quantum dot.

Examples of materials that can be used for an organic compound include a fluorescent material and a phosphorescent material. In addition, examples of materials that can be used for a quantum dot include a colloidal quantum dot material, an alloyed quantum dot material, a core-shell quantum dot material, and a core quantum dot material.

In the display device 700 illustrated in FIG. 13, an insulating film 730 covering part of the conductive film 772 is provided over the planarization insulating film 770. Here, the light-emitting element 782 is a top-emission light-emitting element including the conductive film 788, which transmits light. Note that the light-emitting element 782 may have a bottom-emission structure in which light is emitted to the conductive film 772 side or a dual-emission structure in which light is emitted to both the conductive film 772 side and the conductive film 788 side.

The coloring film 736 is provided in a position overlapping with the light-emitting element 782, and the light-blocking film 738 is provided in a position overlapping with the insulating film 730, in the lead wiring portion 711, and in the source driver circuit portion 704. The coloring film 736 and the light-blocking film 738 are covered with the insulating film 734. A space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that a structure without the coloring film 736 may also be employed in the case where the EL layer 786 is formed into an island shape per pixel or a stripe shape per pixel column, i.e., formed by separate coloring.

Structure Example of Display Device Provided with Input/Output Device

An input/output device may be provided in the display device 700 illustrated in FIG. 11 to FIG. 13. Examples of the input/output device include a touch sensor.

FIG. 14 illustrates a structure in which the display device 700 illustrated in FIG. 12 is provided with a touch panel 791, and FIG. 15 illustrates a structure in which the display device 700 illustrated in FIG. 13 is provided with the touch panel 791.

The touch panel 791 illustrated in FIG. 14 and FIG. 15 is provided between the second substrate 705 and the coloring film 736. The touch panel 791 is formed on the second substrate 705 side before the coloring film 736 is formed. The touch panel 791 is provided between the second substrate 705 and the first substrate 701 and thus can be referred to as an in-cell touch panel.

The touch panel 791 includes an electrode 793, an electrode 794, an insulating film 795, and an electrode 796 between an insulating film 792 covering the light-blocking film 738 and an insulating layer 797. A change in the capacitance between the electrode 793 and the electrode 794 that can be caused when a sensing target such as a finger or a stylus approaches can be sensed, for example.

An intersection portion of the electrode 793 and the electrode 794 is illustrated in a portion overlapping with the light-blocking film 738. Through opening portions provided in the insulating film 795, the electrode 796 is electrically connected to the two electrodes 793 between which the electrode 794 is interposed. Note that the intersection portion may be formed in the lead wiring portion 711 or the like, for example.

The electrode 793 and the electrode 794 are preferably provided in a region not overlapping with the light-emitting element 782 or the liquid crystal element 775, e.g., a portion overlapping with the light-blocking film 738. For example, the electrode 793 and the electrode 794 can have a mesh shape. Accordingly, a structure in which light emitted from the light-emitting element 782 or light transmitting the liquid crystal element 775 is not blocked can be obtained and a reduction in luminance due to the provision of the touch panel 791 can be inhibited, so that a display device with high visibility and reduced power consumption can be achieved. Furthermore, at this time, a low-resistance metal material can be used for the electrode 793 and the electrode 794. Therefore, the sensitivity of the touch panel can be increased compared with a case where a conductive material with a light-transmitting property is used.

Note that the structure of the touch panel is not limited to an in-cell type, and a touch panel formed over the display device 700, what is called an on-cell touch panel, or a touch panel attached to the display device 700, what is called an out-cell touch panel, may be used.

At least part of the structure examples, the drawings corresponding thereto, and the like exemplified in this embodiment can be implemented in combination with the other structure examples, the other drawings corresponding thereto, and the like as appropriate.

At least part of this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

Embodiment 3

In this embodiment, a display device that includes a semiconductor device of one embodiment of the present invention is described with reference to FIG. 16.

The display device in FIG. 16(A) includes a pixel portion 502, a driver circuit portion 504, protection circuits 506, and a terminal portion 507. Note that a structure in which the protection circuits 506 are not provided may be employed.

The transistor of one embodiment of the present invention can be used as transistors included in the pixel portion 502 and the driver circuit portion 504. The protection circuits 506 may also use the transistor of one embodiment of the present invention.

The pixel portion 502 includes a plurality of pixel circuits 501 that drive a plurality of display elements that are arranged in X rows and Y columns (X and Y each independently represent a natural number of 2 or more).

The driver circuit portion 504 includes driver circuits such as a gate driver 504 a that outputs a scanning signal to gate lines GL_1 to GL_X and a source driver 504 b that supplies a data signal to data lines DL_1 to DL Y. The gate driver 504 a includes at least a shift register. The source driver 504 b is formed using a plurality of analog switches, for example. In addition, the source driver 504 b may be formed using a shift register or the like.

Note that the terminal portion 507 refers to a portion provided with terminals for inputting power, control signals, and image signals to the display device from external circuits.

The protection circuit 506 is a circuit that makes, when a potential out of a certain range is applied to the wiring connected to the protection circuit, the wiring and another wiring be in conduction state. The protection circuit 506 illustrated in FIG. 16(A) is connected to various kinds of wirings such as scanning lines GL, which are wirings between the gate driver 504 a and the pixel circuits 501, and the data lines DL, which are wirings between the source driver 504 b and the pixel circuits 501.

The gate driver 504 a and the source driver 504 b may each be provided over a substrate over which the pixel portion 502 is provided, or a substrate over which a gate driver circuit or a source driver circuit is separately formed (e.g., a driver circuit board formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the substrate by COG or TAB (Tape Automated Bonding).

Here, FIG. 17 illustrates a configuration different from that in FIG. 16(A). In FIG. 17, a pair of source lines (e.g., a source line DLa1 and a source line DLb1) is provided so that a plurality of pixels arranged in the source line direction are interposed therebetween. In addition, two adjacent gate lines (e.g., a gate line GL_1 and a gate line GL_2) are electrically connected to each other.

Furthermore, pixels connected to the gate line GL_1 are connected to one of the source lines (such as the source line DLa1 or a source line DLa2), and pixels connected to the gate line GL_2 are connected to the other source line (such as the source line DLb1 or a source line DLb2).

In such a configuration, two gate lines can be selected concurrently. Accordingly, one horizontal period can have a length twice that in the configuration illustrated in FIG. 16(A). Thus, this facilitates an increase in resolution and an increase in screen size of a display device.

Furthermore, the plurality of pixel circuits 501 illustrated in FIG. 16(A) and FIG. 17 can have the configuration illustrated in FIG. 16(B), for example.

The pixel circuit 501 illustrated in FIG. 16(B) includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The data line DL_n, the scanning line GL_m, a potential supply line VL, and the like are connected to the pixel circuit 501.

The potential of one of a pair of electrodes of the liquid crystal element 570 is set in accordance with the specifications of the pixel circuit 501 as appropriate. The alignment state of the liquid crystal element 570 is set depending on written data. Note that a common potential may be supplied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Moreover, a different potential may be supplied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

The pixel circuit 501 illustrated in FIG. 16(C) includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The data line DL_n, the scanning line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like are connected to the pixel circuit 501.

Note that a high power supply potential VDD is supplied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is supplied to the other.

At least part of the structure examples, the drawings corresponding thereto, and the like exemplified in this embodiment can be implemented in combination with the other structure examples, the other drawings corresponding thereto, and the like as appropriate.

At least part of this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

Embodiment 4

In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

In a display module 6000 illustrated in FIG. 18(A), a display device 6006 to which an FPC 6005 is connected, a frame 6009, a printed circuit board 6010, and a battery 6011 are provided between an upper cover 6001 and a lower cover 6002.

The display device manufactured using one embodiment of the present invention can be used for the display device 6006, for example. With the display device 6006, a display module with extremely low power consumption can be achieved.

The shape and size of the upper cover 6001 and the lower cover 6002 can be changed as appropriate in accordance with the size of the display device 6006.

The display device 6006 may have a function of a touch panel.

The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function of a heat dissipation plate, or the like.

The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like.

FIG. 18(B) is a schematic cross-sectional view of the display module 6000 with an optical touch sensor.

The display module 6000 includes a light-emitting portion 6015 and a light-receiving portion 6016 which are provided on the printed circuit board 6010. Furthermore, a pair of light guide portions (a light guide portion 6017 a and a light guide portion 6017 b) are provided in a region surrounded by the upper cover 6001 and the lower cover 6002.

The display device 6006 overlaps with the printed circuit board 6010 and the battery 6011 with the frame 6009 therebetween. The display device 6006 and the frame 6009 are fixed to the light guide portion 6017 a and the light guide portion 6017 b.

Light 6018 emitted from the light-emitting portion 6015 travels over the display device 6006 through the light guide portion 6017 a and reaches the light-receiving portion 6016 through the light guide portion 6017 b. For example, blocking of the light 6018 by a sensing target such as a finger or a stylus enables detection of touch operation.

A plurality of light-emitting portions 6015 are provided along two adjacent sides of the display device 6006, for example. A plurality of light-receiving portions 6016 are provided so as to face the light-emitting portions 6015. Accordingly, information about the position of touch operation can be obtained.

As the light-emitting portion 6015, a light source such as an LED element can be used, for example, and it is particularly preferable to use a light source emitting infrared rays. As the light-receiving portion 6016, a photoelectric element that receives light emitted from the light-emitting portion 6015 and converts it into an electrical signal can be used. A photodiode that can receive infrared rays can be favorably used.

With the use of the light guide portion 6017 a and the light guide portion 6017 b which transmit the light 6018, the light-emitting portion 6015 and the light-receiving portion 6016 can be placed under the display device 6006, and a malfunction of the touch sensor due to external light reaching the light-receiving portion 6016 can be suppressed. Particularly when a resin which absorbs visible light and transmits infrared rays is used, a malfunction of the touch sensor can be more effectively inhibited.

At least part of this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

Embodiment 5

In this embodiment, electronic devices each including a display device manufactured using one embodiment of the present invention are described.

FIG. 19(A) is a diagram showing appearance of a camera 8000 to which a finder 8100 is attached.

The camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, and the like. A detachable lens 8006 is attached to the camera 8000.

Note that the lens 8006 and the housing may be integrated with each other in the camera 8000.

The camera 8000 can take images by the press of the shutter button 8004 or touch on the display portion 8002 serving as a touch panel.

The housing 8001 includes a mount including an electrode, so that, in addition to the finder 8100, a stroboscope or the like can be connected to the housing.

The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

The housing 8101 is attached to the camera 8000 with a mount engaging with a mount of the camera 8000. The finder 8100 can display a video received from the camera 8000 and the like on the display portion 8102.

The button 8103 serves as a power button or the like.

The display portion 8002 of the camera 8000 and the display portion 8102 of the finder 8100 can use a display device of one embodiment of the present invention. Note that a finder may be incorporated in the camera 8000.

FIG. 19(B) is a diagram showing appearance of a head-mounted display 8200.

The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. A battery 8206 is incorporated in the mounting portion 8201.

The cable 8205 supplies electric power from the battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like and can display received video information on the display portion 8204. The main body 8203 is provided with a camera, and data on the movement of the user's eyeball and eyelid can be used as an input means.

The mounting portion 8201 may include a plurality of electrodes capable of sensing current flowing in response to the movement of the user's eyeball in a position in contact with the user to achieve a function of recognizing the user's sight line. A function of monitoring the user's pulse with the use of current flowing through the electrodes may be achieved. The mounting portion 8201 may include various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor to have a function of displaying the user's biological information on the display portion 8204 or a function of changing a video displayed on the display portion 8204 in accordance with the movement of the user's head.

The display portion 8204 can use the display device of one embodiment of the present invention.

FIGS. 19(C), 19(D), and 19(E) are diagrams showing appearance of a head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixing unit 8304, and a pair of lenses 8305.

A user can see display on the display portion 8302 through the lenses 8305. Note that the display portion 8302 is preferably curved and placed, in which case the user can feel a high realistic sensation. When another image displayed in a different region of the display portion 8302 is viewed through the lenses 8305, three-dimensional display using parallax or the like can also be performed. Note that the configuration is not limited to that in which one display portion 8302 is provided, and two display portions 8302 may be provided so that one display portion is provided for one eye of the user.

Note that the display device of one embodiment of the present invention can be used in the display portion 8302. The display device including the semiconductor device of one embodiment of the present invention has an extremely high resolution; thus, even when a video is magnified using the lenses 8305 as in FIG. 19(E), the user does not perceive pixels, and a more realistic video can be displayed.

Electronic devices illustrated in FIG. 20(A) to FIG. 20(G) include a housing 9000, a display portion 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, a chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, gradient, oscillation, a smell, or infrared rays), a microphone 9008, and the like.

The electronic devices illustrated in FIG. 20(A) to FIG. 20(G) have a variety of functions. For example, the electronic devices can have a function of displaying a variety of data (a still image, a moving image, a text image, and the like) on the display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of controlling processing with the use of a variety of software (programs), a wireless communication function, and a function of reading out and processing a program or data stored in a recording medium. Note that the functions of the electronic devices are not limited thereto, and the electronic devices can have a variety of functions. The electronic devices may include a plurality of display portions. The electronic devices may each include a camera or the like and have a function of taking a still image or a moving image and storing the taken image in a recording medium (external or incorporated in the camera), a function of displaying the taken image on the display portion, or the like.

The details of the electronic devices illustrated in FIG. 20(A) to FIG. 20(G) will be described below.

FIG. 20(A) is a perspective view showing a television device 9100. The television device 9100 can include the display portion 9001 having a large screen size of, for example, 50 inches or more, or 100 inches or more.

FIG. 20(B) is a perspective view showing a portable information terminal 9101. For example, the portable information terminal 9101 can be used as a smartphone. Note that the portable information terminal 9101 may be provided with the speaker 9003, the connection terminal 9006, the sensor 9007, or the like. The portable information terminal 9101 can display characters and image information on its plurality of surfaces. FIG. 20(B) shows an example in which three icons 9050 are displayed. Information 9051 indicated by dashed rectangles can be displayed on another surface of the display portion 9001. Examples of the information 9051 include notification of reception of an e-mail, a message of SNS, or an incoming call, the title and sender of an e-mail, a message of SNS, or the like, the date, the time, remaining battery, and the reception strength of an antenna. Alternatively, the icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

FIG. 20(C) is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, an example in which information 9052, information 9053, and information 9054 are displayed on different surfaces is shown. For example, a user can check the information 9053 displayed in a position that can be observed from above the portable information terminal 9102, with the portable information terminal 9102 put in a breast pocket of his/her clothes. The user can see the display without taking out the portable information terminal 9102 from the pocket and decide whether to answer the call, for example.

FIG. 20(D) is a perspective view showing a watch-type portable information terminal 9200. For example, the portable information terminal 9200 can be used as a smart watch. The display surface of the display portion 9001 is curved and provided, and display can be performed along the curved display surface. Mutual communication between the portable information terminal 9200 and, for example, a headset capable of wireless communication enables hands-free calling. With the connection terminal 9006, the portable information terminal 9200 can perform mutual data transmission with another information terminal and charging. Note that the charging operation may be performed by wireless power feeding.

FIGS. 20(E), 20(F), and 20(G) are perspective views showing a foldable portable information terminal 9201. FIG. 20(E) is a perspective view of an opened state of the portable information terminal 9201, FIG. 20(G) is a perspective view of a folded state thereof, and FIG. 20(F) is a perspective view of a state in the middle of change from one of FIG. 20(E) and FIG. 20(G) to the other. The portable information terminal 9201 is highly portable in the folded state and is highly browsable in the opened state because of a seamless large display region. The display portion 9001 of the portable information terminal 9201 is supported by three housings 9000 joined by hinges 9055. For example, the display portion 9001 can be folded with a radius of curvature of greater than or equal to 1 mm and less than or equal to 150 mm.

Electronic devices exemplified below include a display device of one embodiment of the present invention in a display portion. Thus, the electronic device achieves high resolution. In addition, the electronic devices can achieve both high resolution and a large screen.

The display portion of the electronic device of one embodiment of the present invention can display a video with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

Examples of the electronic devices include a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game console, a portable information terminal, and an audio reproducing device, in addition to electronic devices with a relatively large screen, such as a television device, a laptop personal computer, a monitor device, digital signage, a pachinko machine, or a game machine.

The electronic device or lighting device using one embodiment of the present invention can be incorporated along a flat surface or a curved surface of an inside wall or an outside wall of a house or a building, an interior or an exterior of a car, or the like.

FIG. 21(A) shows an example of a television device. In a television device 7100, a display portion 7500 is incorporated in a housing 7101. Here, a structure in which the housing 7101 is supported by a stand 7103 is illustrated.

Operation of the television device 7100 illustrated in FIG. 21(A) can be performed with an operation switch provided in the housing 7101 or a separate remote controller 7111. Alternatively, a touch panel may be used for the display portion 7500, and the television device 7100 may be operated by touch on the touch panel. The remote controller 7111 may be provided with a display portion in addition to operation buttons.

Note that the television device 7100 may include a television receiver and a communication device for a network connection.

FIG. 21(B) illustrates a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. In the housing 7211, the display portion 7500 is incorporated.

FIGS. 21(C) and 21(D) show examples of digital signage.

Digital signage 7300 illustrated in FIG. 21(C) includes a housing 7301, the display portion 7500, a speaker 7303, and the like. Furthermore, the digital signage can include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, a variety of sensors, a microphone, and the like.

FIG. 21(D) is digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 includes the display portion 7500 provided along a curved surface of the pillar 7401.

The larger display portion 7500 can increase the amount of data that can be provided at a time and attracts more attention, so that the effectiveness of the advertisement can be increased, for example.

A touch panel is preferably used in the display portion 7500 so that the user can operate the digital signage. Thus, the digital signage can be used for not only advertising but also providing information that the user needs, such as route information, traffic information, and an information map of a commercial facility.

As illustrated in FIGS. 21(C) and 21(D), it is preferable that the digital signage 7300 or the digital signage 7400 can work with an information terminal 7311 such as user's smartphone through wireless communication. For example, information of an advertisement displayed on the display portion 7500 can be displayed on a screen of the information terminal 7311. By operation of the information terminal 7311, display on the display portion 7500 can be switched.

It is possible to make the digital signage 7300 or the digital signage 7400 execute a game with the use of the information terminal 7311 as an operation means (controller). Thus, an unspecified number of users can join in and enjoy the game concurrently.

The display portion 7500 in FIGS. 21(A) to 21(D) can use the display device of one embodiment of the present invention.

The electronic devices of this embodiment each include a display portion; however, one embodiment of the present invention can also be used in an electronic device without a display portion.

At least part of this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

REFERENCE NUMERALS

100, 100A: transistor, 102: substrate, 103, 104, 110, 116, 118: insulating layer, 106, 112, 120 a, 120 b, 131: conductive layer, 108: semiconductor layer, 108 n: region, 110 f: insulating film, 114: metal oxide layer, 114 f: metal oxide film, 130: display region, 141 a, 141 b, 142: opening portion 

The invention claimed is:
 1. A semiconductor device comprising a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a semiconductor layer, and a first conductive layer, wherein the second insulating layer is positioned over the first insulating layer, wherein the semiconductor layer is positioned over the second insulating layer and has an island shape, wherein the third insulating layer and the first conductive layer are stacked over the semiconductor layer, wherein the second insulating layer has an island shape having an end portion outside a region overlapping with the semiconductor layer, wherein the fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, is in contact with part of a top surface of the semiconductor layer, and is in contact with the first insulating layer outside the end portion of the second insulating layer, wherein the fourth insulating layer is in contact with a top surface of the second insulating layer and not in contact with a side surface of the second insulating layer, wherein the semiconductor layer comprises a metal oxide, wherein each of the second insulating layer and the third insulating layer comprises an oxide, wherein the first insulating layer comprises a metal oxide or a nitride, and wherein the fourth insulating layer comprises a metal nitride.
 2. The semiconductor device according to claim 1, wherein the fourth insulating layer comprises aluminum.
 3. The semiconductor device according to claim 1, wherein the first insulating layer comprises oxygen and at least one of aluminum and hafnium.
 4. The semiconductor device according to claim 1, wherein the second insulating layer and the semiconductor layer have substantially the same top surface shape.
 5. The semiconductor device according to claim 1, wherein the end portion of the second insulating layer comprises a portion positioned outside a region overlapping with the first conductive layer.
 6. The semiconductor device according to claim 1, wherein the end portion of the second insulating layer comprises a portion positioned in a region overlapping with the first conductive layer.
 7. The semiconductor device according to claim 1, wherein the second insulating layer is thicker than the first insulating layer, and wherein the second insulating layer is thicker than the semiconductor layer.
 8. The semiconductor device according to claim 1, wherein a bottom surface of the second insulating layer is aligned with a bottom surface of the fourth insulating layer, and wherein a top surface of the first insulating layer is aligned with a bottom surface of the second insulating layer and the fourth insulating layer.
 9. The semiconductor device according to claim 1, wherein, in a top view, the second insulating layer extends beyond an end portion of a first wiring electrically connected to one of a source and a drain of a transistor, wherein the end portion of the first wiring does not overlap with the semiconductor layer, wherein, in the top view, the second insulating layer extends beyond an end portion of a second wiring electrically connected to other of the source and the drain of the transistor, and wherein the end portion of the second wiring does not overlap with the semiconductor layer.
 10. The semiconductor device according to claim 1, wherein, in a cross-sectional view, the third insulating layer is in contact with the second insulating layer.
 11. The semiconductor device according to claim 10, wherein, in the cross-sectional view, the third insulating layer is in contact with a side surface of the semiconductor layer.
 12. The semiconductor device according to claim 1, further comprising a second conductive layer under the first insulating layer, wherein the second conductive layer comprises a region overlapping with both the semiconductor layer and the first conductive layer.
 13. The semiconductor device according to claim 12, wherein the end portion of the second insulating layer comprises a portion positioned outside a region overlapping with the second conductive layer.
 14. The semiconductor device according to claim 12, wherein the end portion of the second insulating layer comprises a portion positioned in a region overlapping with the second conductive layer.
 15. A semiconductor device comprising a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a semiconductor layer, and a first conductive layer, wherein the second insulating layer is positioned over the first insulating layer, wherein the semiconductor layer is positioned over the second insulating layer and has an island shape, wherein the third insulating layer and the first conductive layer are stacked over the semiconductor layer, wherein the second insulating layer has an island shape having an end portion outside a region overlapping with the semiconductor layer, wherein the fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, is in contact with part of a top surface of the semiconductor layer, and is in contact with the first insulating layer outside the end portion of the second insulating layer, wherein the fourth insulating layer and the second insulating layer have substantially a same thickness, wherein the semiconductor layer comprises a metal oxide, wherein each of the second insulating layer and the third insulating layer comprises an oxide, wherein the first insulating layer comprises a metal oxide or a nitride, wherein, in a cross-sectional view, the third insulating layer is in contact with the second insulating layer, wherein the fourth insulating layer comprises a metal nitride.
 16. The semiconductor device according to claim 15, wherein a bottom surface of the second insulating layer is aligned with a bottom surface of the fourth insulating layer, and wherein a top surface of the first insulating layer is aligned with a bottom surface of the second insulating layer and the fourth insulating layer.
 17. The semiconductor device according to claim 15, wherein, in the cross-sectional view, the third insulating layer is in contact with a side surface of the semiconductor layer. 